In digital frequency synthesizers, there is a need for a variable divider which counts the cycles of an input signal having a given frequency until a predetermined number of counts have been accumulated. The size of the count is usually referred to by the letter N. Once N counts have been accumulated, the variable divider is reset to begin the cycle again. It is desirable for the number of counts N to be variable in order that it can be programmed in advance of each count by means of a control input.
When N is large and the operating frequency of the counter is to be high, technical difficulties can arise in constructing a multistage high frequency variable divider. In the prior art, the problem is typically overcome by using a fixed high frequency divide by M stage prior to a variable divide by N stage. This solution is not always desirable because the total division factor can only be a multiple of M.
In a digital frequency synthesizer application, it is usually desirable to be able to program the total division factors in steps or increments of 1. The steps, therefore, relate to the frequency resolution or the frequency step size of the synthesizer. If the divider is only programmable in steps of M, the frequency steps available are relatively coarse and determined by the factor M.
Another approach to the problem is to begin with a high frequency divider stage or prescaler while retaining the ability to program the divider count cycle length in steps of 1. This arrangement allows the prescaler to be varied between dividing ratios of R and R+1.
It is possible, for example, for a dual ratio prescaler having the division ratios 10 and 11 to perform a division of 157. The number 157 can be expressed by the equation 7.times.11+(15-7).times.10. The prescaler is first programmed to divide by 11, and the lower frequency divider stage is set to count 7 prescaler output pulses. After counting 7 prescaler output pulses, the prescaler is set to divide by 10. The low frequency divider stage is then set to count 8 prescaler output pulses. Upon completion of this count, a total of 7.times.11+8.times.10=157 input pulses have been applied to the prescaler input. The cycle is then begun again. It should be noted that in order to obtain numbers in steps of 1, the number of times the prescaler divides by 11 must be programmed from 0 to 9 and the number of 10's in the total number must not be less than 9. This relationship sets a lower bound of R(R-1) for the contiguous number range that can be achieved with a two ratio prescaler having ratios R and R+1.
The most common method employed to count two different numbers of prescaler output pulses, N1 and N2, while the prescaler is dividing respectively by ratios R1 and R2, is to use two separate low frequency down counters that are preset to the values N1 and N1+N2, respectively. For example, the division of 157 with the aid of a 10/11 prescaler could be achieved by presetting one divider to N=7 and the other to N1+N2=15. The prescaler would then first be set to divide by R1(11) while both low frequency counters counted down on the prescaler output pulses. When the N1 counter reaches zero after 7 prescaler output pulses, the prescaler would switch and divide by 10, and the N2 counter would continue to count down a further 8 prescaler output pulses until it reaches zero, completing the cycle. This system has the advantage that a desired division number is simply expressed in values to which the N1 and N2 counters can be preset. This arrangement has the disadvantage that two variable dividers are required and power consumption is increased when both dividers are operating. Increased power consumption is a significant disadvantage for battery powered equipment.
U.S. Pat. No. 4,053,739 describes a single variable divider that is alternatively programmed with the value N1 when the prescaler divides by the value R1 and is programmed with the value N2 when the prescaler divides by the value R2. This device has the advantage that a single variable divider suffices. Unfortunately, the described arrangement includes additional circuit complexity in the form of a multi-line switch. The multi-line switch alternately selects the bits corresponding to the values N1 and N2 in order to preset the single variable divider. Although this additional circuitry operates at a lower power consumption than a circuit having two variable dividers, it still requires substantially the same amount of circuitry when implemented as an integrated circuit.
Accordingly, there is a need for a counter for a programmable divider which can register both the counts N1 and N2 without them being presented alternately to the counter. This arrangement would eliminate the need for a complex multi-line switch.